Video compression and decompression standards, such as H.264, VC-1, MPEG-4, MPEG-2, and JPEG, use variable-length codes, hence require a variable-length code decoding apparatus in a decoding system. However, a variable-length code decoding process has a difficulty in decoding a plurality of variable-length codes in parallel, which tends to be a bottleneck in a processing performance of a decoding system.
In general, for an image of standard definition (SD), it is enough to decode one symbol for each clock cycle. However, as a display resolution becomes higher from high definition (HD) to super high vision, a higher decoding efficiency is required, hence there is a demand for improving the processing performance so that a plurality of variable-length codes per clock cycle can be decoded.
There are proposals for decoding a plurality of variable-length codes within the same clock cycle (referring to patent documents 1 and 2). However, there are problems in the proposals, such as the difficulty in increase in operating frequency and the dependency of decoding performance on the appearance pattern of variable-length codes.